Sampled data controller

ABSTRACT

A sampled data feedback controller includes means for deriving a plurality of error signals within a single control formulation time interval. The error signals are derived by comparing the response of a plant with a reference input, constant over the interval, in a servo subtraction node. Each of the sampled errors is applied to an accumulator with a weighting factor, having a value selected on a predetermined basis, determined by the plant characteristics, to provide finite plant settling time. At the end of each control formulation interval the previous output of the accumulator is fed back to the accumulator, through a weighting factor network. The output of the accumulator at the end of each formulation interval is applied as a control input to the plant. In a specifically disclosed embodiment, the plant is a spin stabilized, attitude controlled satellite.

v km p 5m -EugmeG.Bo In] h emor Bou-iqtd 411-1114: Emmirzr-R. StephenDEdineJr. [2!] AppLNo. 28.984 A1!on1:ysiLF.K= P .E lzvyandmlMcCoy [22]Filed May 29, 1969 [45] Patented May 18, I97! [73] Assignee The UnitedStates of Americ: I:

represented by the Admlnistrmrd lb:

Aeronautic and Space I 1 AmACl'zAampleddatafeedback controllerixdude:muforderivingapltnlityoferrorflgnalswithinafingle control fu-mulatisntime interval. The error signk are {54] 'w derived by comparing theresporse of a plant with a rd'exeme I M ainptmmxtovermeinten-aljnnervombtnctionnode. [52] US. Cl 235/150-1, Eachof the sampled error: is applied In an accumulator with a 235/1511,235/l50.27. 235/ 150.2 weighting factor, having a value selected on apredetczmhaed [51] InLCl. 605%: 21/ 2- Enskdclnminedbytheplamcharacterisfics.top1ovidefmhe GOSb ll/lO,G05d 1/08 plantsettlhgtime. At theendot'each control formulafionin- [$0] FieiddSeud1 235N501,terval the previcxs output of the acwmulator '5 (ed had: to

1os1,1so.2s.1so.4.1s1.1,151.11 a mamaiagor, through a weighting factor mThe 4 outpmoftheaocumulatorattheendofeachfommlafiouin- 1tewalisawiiedaaommlinputtotlzplantlnaspedfimlly UNITEDS'IATES PATENTSdisclosed embodimem, the plant 11 u msabimm 3.460.096 8/1969 Barron340/1715 l d ll I 1 1 1s '7 14 ssmAL ay 9 I MCUMULHOQ ,L4 T OLD PLAN, 1l 1 80 1. III

Patenied May 18, 1911 5 sgmwsheu z 6! uomz.

DEL subset a r SYNC. MOTOR.

B5 Bl SRWEZ 4BR SIR.

- INVENTOK JWEsA 6mm f Qkx lead for deriving mch controller outputsignal.

SAMPLE!) DATA coh'nzoun ORIGIN OF INVENTION The invention describedherein was made by an employee of the United States Government and maybe manufactured 5 and used by or for the Government for governmentalpurines without the payment of any royalties thereon or therefor.

nrmooucnohl control signal. l5

Presently known data controllers generally include means for deriving acontrol signal that is updated at intervals equal to or smaller than thetime between derivation of error samples. In other words. prior ansampled data controllers normally include means for sampling a referencesignal and an output signal ofa plant being controlled at the same rateas input signals are applied to the plant; in the alternative, controlsignals are applied to the plant at a rate greater than the nmpling rateof an error signal responsive to a reference input and a plant outputresponse. Because of this factor, prior art sampled data controllersgenerally employ a plurality of memory elements for storing amultiplicity of gut sampled errors that are utilized to derive a controlsignal for the plant. Because a plurality of memory elements aregenerally utilized with prior art sampled data controllers. suchcontrollers tsually have relatively complex hardware implementation.

in accordance with the present invention. a sampled data mntroller isprovided wherein an error signal is sampled a plu-- rality of timeswithin a single control formulation interval to derive a single eehrmrsignal. The control signal durin any control period is derived byintegrating or acaunulating. value: proportional toerror signals sampledduring the control periodandthepreviouscontrolsignaL'l'heerrorandpreviom I conu'ol signals are modified by suitableweighting factors deiehhihed by a plant being controlled. with theweighting factors for dili'erent samples being variable as a function clthe sample number within the control period. Preferably. the weightingfactors are selected to provide finite settling time fcrtheplantresponsetoadisturbanceintheplantdynamic 5 state and to minimize inputnoise transmision. Finite settling tirneforaplantrcsponsemeansthataplanbevenonehavirg timeleadandlagcharacteristiqcanbebroughttoaequilibrium point after being dismrbed from an initial condition withina finite, rather than infinite. time interval.

It is characteristic of systems properly dmigned in accordance with thepresent invention that the transient resporse. governed by the finitesettling time, is independem ofthe amount ofnoise filtering imposed onthe system by the controller. Hence, a plant driven by a controller inamordance with the present invention can be driven to an output valuewithin a predetermined plurality of control intervals independently ofthe filtering time necesary to remove noise. Thisfeamreisincontrastwithmostpriorartsysternswhereinfillarly taming optics!pickup on the satellite derive signak indicative of the satelliteattitude. 'l'hese variable position signals are compared with areference pulse train to derive variable pulse width or duration errorsignals. The error signal: are weighted a a function of time within acontrol formulation interval. The weighted signals are stored in anaccumeiatcr reg ner which drives a digital-to-analog converter upon thecompletion of each control Formulation interval. The digItal-to-aralogconverter output is applied as the control input to a magnetic torquerfor the satellite attitude control. For the particular appliation, ithas been found that by utilir'ng four error samples within each controlrt'gzal interval nearly minimum no'se sensitivity and finite settlingtime of two control signal intervals can be attained with a relativelysimple implementation.

it is, accordbngly. an object of the present invention to provide a newand improved sampled data feedback controller.

Another object of the present invention is to provide a new and improvedsampled data feedback controller wherein noise filtering is independentof transient Anadditional objcctofthe present ihvehrieh istoprovidea newand improved sampled data fwdbaclt controller utilizing relativelysimple digital hardware.

Anorherobject ol'the invention istoprovidear-ewand iroproved sampleddata feedback controller wherein an em: signal is sampled a pluralityoftirnes during each formulation ol'aconu-cl signal.

Stillml'ierobjecsol'the presentinventionistoprovidea sampled datafwdback controller wherein weighted coeflicients for sampled errors anda controller feedback input are selected in; predetermined manner,dependent upon characteristics d a plant being controlled, to enablefinite settling timeandahighdegreeofnoisefilteringtobeobtained.

Stillaootherobjectofthepresentinvention istoprovidea new and improvedsystem for controlling the attitude of: satellite 'norbit.

Still aftn therobjeetotthe inventionistoprovideanewand improved systemfor controlling the attitude of a oartwl'ieel Qtellite wherein thesatellite ha a finite settling time and system note in: virtually aminimum efi'ect.

'lheaboveand still furtherobjects, featuresand advantage: of the praartinvention will become apparent upon consideration of the followingdetailed desu'iption ofooe MIC embodiment thereof. especially when takenin coojtmcticn with the accompanying drawings, wherein:

BRlEF DESCRlPTlON OF THE DRAWINGS FIG; 1 I a block diagram illustratrn'g the primrpls' of the presentirrvention in broad terns;

HO. 2 is a perspective view of a cartwheel satellite stabiLinaccordancewiththeprinciplenofthepresentinveation;

fiGllissdrcuitdiagramfortheerrornehworkinthe digitalcmtrokrofthe systemofFlG. 2;

[-10.4arewavel'orrrrsutilized todescribetheoperationof thesystemofFlG.3;

HG.$isacireuit.bLoekdiagramo(asequeneeconuoller te'ing time andtransient respome time are interrelated with 50 {mmcumqofflazlmd eachother so tl'm a fast transient resporee '5 usually an sedated with poornoise filtering response and vice versa. Controllers milling theprinciples of the present can be provided with a fast transient responseand adverse eftion of the weighting coefficients. A further advantage ofthe present invention is that the complexity and amount of hardwareutilized can be reduced relative to prior art sample data controllerssince only a single memory element need be util- In accordance with citespecifically disclosed embodiment of the invention, the principlesthereof are applied to an attitude controller for a spin stabilizedcartwhx'satellite, that is. a satellite having its spin axis maintainedmrrnal to the FlG.6isacircuit, block diagramofanaccumtllatorandwei'ghtingfzctor network for the PEG. Zeontroller.

' DETAILED DESCRli'llON ornrs oruwmcs wherein a plant 11 to becontrolled is responsive to a con troller lie-ad a reference inputsignalon line 13. Piant It includes means for deriving an output signal.C. on line 14indicativerrfacharecterirticthcreofisuchorpositiortTbehiputversuswtpctrrsponseofplantllissuehthattheplantcanbe represented by a setof linear differer" equations having real. but not necesarily finite,eigenvalues so that certain attenuation or fizctors within controller 12can be selected t u-sablctl'esplant to haveafinite settlingtimeand'satellite orbital plane. Pulses derived in an angu- 5 maximum rob;filterlagie, minimum noise sensitivity.

cally. the output of serial accumulator 23 at the end of acou- Dierespor:se.C.ofplant H is derivedon line 14 and compared with a referenceinput signal. R. on line 13 in subtraction node l5 which derives anerror signal. E. indicative of the difference lxtween the inputs thereof(R-C The error signal derived from node l5 is applied to the input ofcontroller 12 which is also responsive to the input signal, U, for plantII. The input s' l to plant ll is derived by periodically feeding theoutput of controller [2 to sample and hold network 16. which maintainsthe value of U constant over an entire control-signal formulationinterval of controller 12. fire output of sample and hold network 16 isapplied in parallel to plant ll and to an input terminal of controller12.

The error signals derived from node are applied in sequence during acontrol-siptal formulation interval to weighting factor networks K7,.17,...l7 md 17.. which feed summing node 18. Patch of weighting naworks17,-". is responsive to the error output signal of difference node 15once during each control sigtal interval in response to switches 19,-19.being closed and opened in sequence, at times l,+r,, I31, ...t.+,,,,r.+r., respectively, where t, is time at the beginning of controlformulation interval. Each of switches l9,--l9. is closed at a differentinstant of time and for a relatively short portion of each controlformulation interval of controller l2. 'lhereby. during each controlformulation interval, having a ZT-second period. there are applied a:summing node 15, n sampled error signals occurring at tima 27', 213..21, 21', 1| It I respectively having values of B,E, 8,5... .J E. 8.5.where 8.. 8 .03, and B. are the eoefficimts of networks 17,, 17,...17.and 17., respectively.

Prior to any ofswitehes 19,-!9. beingdcsed at time of B.U. Hence. inresponse to the signals applied to node 18,

the node derives during each control-signal formulationintervalofcontroller l2 asequential sen'esofnmpled signalseach having avalue commensurate with the outputs ofweighting factor networks 11,-".and 22. The signal derived from summing node 18 during the firstsampling period is represen- $0 tativeofthe previous inputcontroltoplart H and hasavalue B U. Immediately after the B.U sample ha beenderived from summing node l8, the first error sample a derived from thesumming node as B E=8;a(RC). After the 8,5 signal is derived from theoutput of summing node 28, switch 19 i openedandswitchl9,iscloseltofeedasipralcommensurate with 8,5 through the summing node.in the foregoing manner, there are derived from summing node 18 aplurality of sanpied errors and. the previous sampled control valueduring each control-signal formulation interval of controller 11.

'lhe sampled outputs ofsumrning node 18 are applied to serialaccumulator 23 which functions eflectively a a finite time integrator.Accumulator 23 is preferably a digital rep'sta' having the countthereofmodified in accordance with the am- 5 plitude and polarity ofeach sample derived from summing node 18 during a control sgnalinterval. At the beginning of ach control formulation interval. thecount stored in serial accumulator 23 is zero; at the end of eachsampling interval U. is the output ofthe serial acarmulator at the endofthe previous control-signal formulation interval.

The signal stored in serial accumulator 23 at the end ofeaeh controlsignal interval is applied through switch 24. at time r,+ 21' (where 2Tis the length of each control formulation interval) to sample and holdnetwork 16 which immediately changes value in accordance therewith.After sample and hold network 16 has responded to the output of serialaccumulator 23, switch 24 is opened and the serial accumulator iscleared to zero. A new sampling interval that commences with the closingofswitch 21 to gate the new value of U in sampleand hold network 16through attenuating network 22 and summing node 18 into serialaccumulator 13. During the new control formulation interval theoperation of eontrollca' 12 continues in the manner described tofeedsampled signa's into serial accumulator 23 and drive plant 11 periodcally with control signals derived from sample and hold network 16. Inresporrsetovariationsintheoutputofa'npleandholdoetwork 16. at the end ofeach control signal interval, plant It is driven in a predictablemanner, governed by its character'stic 5 differential equations.

Aspecil'ic appliation ofthe principlesofthepresent invention is providedwith a system ofthe type illustrated by HG. 2 wherein a cartwheelsatellite 31 is illustrated as being in earth orbit, traveling about theearth it: a circular orbit and the 30 direction indicated by arrow 32.Stabilization of satellite 31 is provided by spinningthe satellite aboutaxis 33, which is maintained mrmaltotheor'oitalplaneofthes'atelliteCarriedon satellite 31am rotating therewith aboutaxis 33 are tamer-a3 andhorizonphotoeell detectorJSwhidtderivesapositive going lading edgeachtimetheqinning satellitepassestheskyearth horizon, i.e., once for each rotation of satellite 3!aboutaxis33atthetirnewhenaskytoeanhtransitionis sensed. Toenablearelatively largeareaonearthtobe viewedbycamera34,thecameraisdrivenataeonstantvelocityaboutasis37.perpendiculartothesatellite spinaxis33,bya synchronous motor(not shown). While cameraJ-isdriventhrougheomplete360'scansaboutaais37theviewingangleofearnera34islimitedbytl'telengthofviewingslot38on satelliteSl.

DesirablyJherotationofcameraMaboutaxisSlJherotationofsatellite3l aboutaxis33andthe movementofthe satellite alongthepathindieatedbylinenaresuchthatthecamerafieldofviewforapairofatceessivesatelliterotationsisdefinedbythetwoadjacent, generallyparallelandnonoverlappinglinescantraelts39.'lhisresultisattainedbyeoutrollingth'emind: of satellite 3! relativetospinasisflwith a magnetic torquer 41respotsive to controller 42,constuctedinlccordaneewiththeteachingsofthepreseminvention Controllerdlisresponsivetoareference frequencyderivedfromanoscillatordrivingthesynchronommforscarmingmrneraunswellasindicativeoftheaogularpoitionofasignalofratellitelllrelativetotheearthsbor'rzon,

derivedbyphotodetectorMJleneeJhereferencesignaLR,

ofFlGJisderivedfi'omthedrivecircuitr'yforcamera3$and theplant lloutpucQisobtair-iedfrom photocell3$.Cootroller 42 responds to thereference drive circuit for camera 34 and the variable outputcfphotoeell 35,'to drivetorque-rfl tophaselockthespinofsatellite3ltotherotationofcamera 34aboutaxis37andenabletheeamera'tompathsinthecount in the serial accumulator is indicative of each ofthe forcesapplied by torquer 41 can be represented as a double sampled errors, asmodified by the weightztg factors 8,-8- athtracted from the previousinput control to plant 11. as modified by the weighting factor ofnetwork 22. Mathematitrol signal interval of 21' can thereby berepresented a:

intep'ation function, having a response proportional to ",2, wheresistheLaPlaeeoperaton'lhegainofthepl-anginchsding proportionality constanuintroduced by sample and hold network IS, the respome of torquer 41 andthe movement of satellite3linresportsetoforcesdevelopedbytlntorqueris apart of the plant. It will be shovm infra that the satellite plant ofHO. 2 can be stabilized in three control-signal formulation intervals.each having a ZT-second length. with very low noise sensitivity byutilizing four error sampling periods in each im terval. selecting andpicking the weighting coefficients in accordance with ratios related to:

Controller 42. in essence. includes a system for deriving pulse widthmodulated signals to indicate the position error between the referenceand control signals derived from the drive for camera 34 and photocell35. During each control intenal. four pulse width modulated errorsignals are derived in sequence and weighted in accordance with theconstans. B B..

During each sample period of the control formulation interval. theoscillator for driving synchronous motor 34 derives wave trains 51 and52, FIG. 4. Wave train 51 includes a short duration pulse having aleading edge coincident with the beginning of each sample time and atrailing edge. to which other circuits in the system are responsive,that occurs almost immediately after the leading edge. in contrast. wavetrain 52 is in the form of a square wave, having equal half-cyclesduring each of the samp e times between adjacent pulses in wave train51. The leading, positive going edge of wave train 52 is synchronizedwith the leading edge of the short duration pulsea of wave train 51while the leading edge of the negative portion ofwave train 52 occursexactly in the middle ofeach sample period.

The output of horizon detector 35 Ba rectangular pulse width modulatedwaveform having a leading, positive going edge coincident with theleading edge of reference waveform 52. The trailing edge of the pulsewidth modulated waveform is indicative of the horizon location andvariable about the reference. midpoint of waveform 52. As the positionof the horizon varies. as sensed by detector 35, the detector derivesvariable position pulses to produce variable duration rectangular waveswithin each of the n sampling periods of each control formulationinterval. For a time lag between the output of detector 35 and thereference drive for camera 34. i.e.. a negative error, the trailing edgeof the variable duration pulse occurs before the midpoint of waveform52. as indicated by waveform 53; in contrast. for the horizon sensorbeing poi tioned ahead of the reference wave driving camera 34, i.e., apositive error, the trailing edge of the variable pulse rectangularvtave is subsequent to the refereree point of waveform 52, as indicatedby waveform 54. For a nero phue error between the reference signalderived from camera 34 and horizon sensing photodetector 35, thephotodetector derives an output signal of identical shape and timeposition as reference waveform 52.

The controller 42 includes cirmitry. described infra, for combiningreference wave form 52 with the variable duration horizon indicatingsignals generated by detector 35 to derive variable duration errorsignals which invariably have a transi tion coincident with thereference point of waveform 52. For a negative error, the variableduration error indicating signal has a negative going transition, asillustrated by waveform 56. coincident with the center of reference wave52, and a positive going transition coincident with the trailing edge ofwaveform 53. For a leading positional error between the horizon sensorand the reference drive for camera 34. the error signal is indicated bywaveform 57, having a leading edge coincident with the midpointtransition of waveform 52 and a trailing edge coincident with thetrailing edge of waveform 54.

For certain control functions it is necessary to indicate when anerrorcycle has been completed. Such an indication is derived by sensingthe leading. positive going transition of a wave train generated inaccordance with the logical operation C-R'. For oegtive and positiveerrors. therefore. the completion of an error cycle is indicated bywaveform $8 and 59, respectively. ln response to the posizivetransitions of waveform $8 or 59. the system is advised that an errorample has been completed and can be processed.

Exemplary circuitry for deriving the puke width modulated errorindicating signals of FIG. 4 is illustrated by HO. 3. In normalOPCTtllOfl. a single sampling period occurs during each rotation ofsatellite 31 so that the satellite rotation rate equals a referencefrequency deri ed from oscillator 64 which drives synchronous motor 62.Motor 62 turns camera 34 about axis 37 with the same frequency a isderived by oscillator 64 and detector 35, e.g. 30 r.p.m. To derivevariable width indicating waveform 53, there is provided shaper 61.regionsive to the positive going leading edge output of detector 35 andthe trailing edge of waveform 51 derived from shaper 65, which is drivenby oscillator 64. Shaper 61, which may be a flip-flop. is aaivated toderive a binary one output in to the trailing. positive going edge ofwaveform 5] fed thereto byshaper 65.1'heoutputofshaper6l istnaintainedat the binary one stzte until a positive transition is fed to the shaperby detector 35. in response to the output of detector the shaper 61output returns to the binary zero level until the next sampling periodcommences. i.e.. in response to a positive going transition in theoutput of shaper 65.

To derive the error signal waveforms S6 and 57, the variable, pulseduration modulated waveform 53 generated by shaper 6l '5 combined withthe oscillator 64 reference waveform $2 in a network including AND gates67 and 68. AND gate 67 is directly responsive to the variable durationwaveform 53 and reference wavefonn 52. while AND gate 68 is responsiveto inverted replicas of these waveforms a derived by inverters 69 and70. Gate 67 thereby derives a binary output eommcnsurate with C'R whilethe output ofAND gate 68 is represented a (Tl t, and has a leading edgeindicating that an error cycle has been completed. The outputs of gats67 and 68 are reversed in phase by inverters 72 and 73. respectively.which derive outputs commensurate with GE and CH1. The outputs ofinverters 72 and 73 are combined with waveftrrn 51. as derived by shaper65 which is driven by oscillator 61. in AND gates 74 and 75. AND gate 74feeds the set input offlip-flop 76, while the reset input of flip-flop76 is a phase inverted replica of the output of AND gate 75. as derivedfrom inverter 77.1. Hip-flop 76 responds to the set and reset inputsthereof to deri e one of the variable duration, pulse width modulatederror waveforms $6 and 57, FIG. 4. do pending upon the error polarity.

The pulse width modulated waveform derived from flip-flop 76, indicativeof the positional error of satellite 3! relative to a referenceposition, is combined with the output of shaper 61 and inverter7t3 inAND gate 77 to enable the polarity ofthe error to be indicated. AND gate77 derives a binary output signal that fwds the set input offlip-fiop78, the reset inputd which is responsive to an inverted replica of theoutput d shaper 76. as derived by inverter 79. ln response to theirtrvts thereof,flip-fbp73isset toastate indicative ofthe signoftheerror, at a time coincident with the completion of an em cycle withineah sampling period. if the error has a positive value, indicated by anegative transition in the output of flipflop 76 after the center ofreference waveform 52, flip-flop 78 55 is set to a binary one stateduring the interval between the completion of the error cycle and thebeginning of the next 'Fffling period The error cycle completion andbeginning of the next sampling period are respectively indicated by theleading edge of waveform 59, as derived from AND gate 68,

and the trailingedge ofthe pulses in wave train 51. lfthecrror isnegative, flip-flop 78 is set to a zero state in response to thetrailing edge of waveform 53 occurring before the negative transition ofwaveform 52. The flip-flop 78 remains in the binary zero state until thebeginning of the neat sampling period,

5 indicated by the trailing edge of each pulse in wave train 51.

To reset flip-flop 78 to a zero state at the beginning of each samplingperiod. the output of shape: 76 is inverted by inverter 79 and appliedto the flip-flop reset input To enable positive voltages indicativeofthe positive and negative polarities of the error sig al to bederived. the output of flip-flop 78 i fed through inverter 81. Thereby.if the output of flip-flop )8 is a binaryone at the end ofeach samplingperiod. an indiation '5 provided ol'a positive error signal. while abinary one derived from inverter 81 at the end of each sampling intervalindicates a neptive error signal.

The circuitry of HG. 3 performs the function of summing node 15. HG.Line: the HG. 3circuit derives output signals indicative of the errorbetween a reference input phase of oscillator 64 and the variableposition indicating output of detector 35. The variable duration errorindiating output signals of HG. 3 are processed in the circuitry of HGS.5 and 6 which perform the functions of switches 19.. 19,. weightingmefi'rcients 3....8, summing node 18. serial accumulator 23 and theremainder of the drive circuitry for plant 11. Broadly. the circuitry ofHGS. 5 and 6 responds to the variable duration. pulse width modulatederror sig lals generated by the circoil of HG. 3 on a time divisionmultiplex basis Each sampled error signal is multiplied in a singlemultiplication network by a predetermined weighting factor. dependingupon the same period number within the control signal interval. Thesingle multiplication retworlr feeds a munter which functions as theserial accumulator. which drives a digital-to-analog wnvcrter. thatfunctions as a sample and hold network and controls the sip-la!amplitude applied to magnetic torquerfl. HG. 2.

The circuitry of HGS. 5 and 6 functions in two sampling modes. 1n thefirst mode. when steady state operation ofthe satellite attitude annotbe presumed but is transient in nature.thepositionalerrorsaresamplcdonlyonceeverynrtherror nrnpling cycle.where m is an integer greater tl'an one. When. however. the system isoperating in a steady state mode. each error cycle is sampled during theformulation of ach control signal. The difference in the sampling rateis provided to enable a register having a relatively small number ofstages to be utilimd without reaching saturation. as would occur if allof the error sampla were sampled during large transient operation. Withthe system in a steady state condition. the system loopgairrislteptconstant by reducingthe plantgainto llnlof the value used with itoperating in a transient state.

Considering now specifimlly the circuitry of H65. 5 and 6. the sequencerof HG. 5 includes a 4-bit shift register 91. withonestageoftheshiftregisterbeingprovidcdforeachofthe sampling periodswithin a control-signal formulation interval. At the end ofeach ofthefour sampling periork. within a control formulation interval, shiftregister 91 is supplied with a shift pulse. To this end. the output ofAND gate 68. H0. 3.

having a leading edge occun'ing upon the completion of an error cycle.is fed through diflerentiator 92 to the reset input of flip-flop 93. andthrough divide by in frequency dividing counter 94 to the set input offlip-flop 93. Thereby, flip-flop 93 is reset once every m error cyclesof the HG. 3 circuitry. The output offlip-flop 93 is fed throughcascaded inverters 9S and 96 to difl'erentiator 97 which feeds a shiftinput into rep'ster 91 in response to each positive transition offlip-flop 93 from the reset tothe set state.

As shift register 91 is stepped between its various flags. a binary oneoutput is derived from the activatd :age. The output of each of the fourshift regiser stages. AD. is applied to the input of a different one ofAND gates 101104. AND

I gates 101-104 are also respons've to a signal indicative ofthe sign orpolarity of the error signal. derived from flip-flop 78. HG. 3. Gates101 and 102 are responsive to thesign or polarity indication of theerror signal directly. while gates 103 and 104 are responsive to aninverted replica of the error signal polarity, as coupled throughinverter 81. Each of AND gates 161-104 drives a separate inverter105-103, the outputs of which are combined in AND gate 109. AND gate 109derives a binary signal indicative of the polarity of the change tn thecontrol signal being formed resulting from the sample being 132.indicative of the desired rate at which error tobetaken'lhebinarysipalonlead 132isderivcdatwilLor verter110isabinaryonesignal.an is providedthatthe polarity of the control signal change is positive. while a binaryaero level output of the inverter indicates a negative change in thecontrol signal. The error signal sign or polarity indicating signalfeeding gates 101-104 is interrelated with the signals derived from thestages A-D ofshift register 91 in accordance with the polarity of the8,...8. weighting Tm Hence. for the B. and 5, positive weightingfactors. the error signal polarity indicaling signal is applied directlyto AND gates 101 and 102. while for the negative B, and B. weightingfactors. an inverted replim of the error signal polarityindicatingsignalisapplied toANDgates103and10-4.

To reset flip-flop 91 after a control interval has been completed, asindicated by the shift-register D stage switching from an activated to adeactivated state. the D state output is coupled through inverter 112 todifl'erentiator 113. Differentiator 113 responds to the output ofinverter 112 to derive a binary one output for a predetermined timeinterval afler the trailing edge of the D stage of the shift register habeen completed. The output of differentiator 113 is coupled to the resetinput of shift register 91. Thereby. shift register 91isresettotheAstageafterthe Dstage thereofhabeendeao tivated.Difl'erentiator 113 also drives a load input terminal of adigilal-to-analog converter. described infra in conjunction with FIG. 6.Thereby the digital-toenalog converter isrcsponsive to a new inputsignal simultaneously with shift register 91 having its A stageactivated.

To control the rate at which error signalsare supplied fromthecircuitofHG.3 tothedrcuitofHG. 6. aswell asthegain of circuitr'ycontrolling magnetic torquer 41. flip-flop 131 is provided. Hip-flop 131is of the rnaster slave or .I-K type. whereby set and reset signals aretransferred to an output terminal oniyinresponse toatrigger signal beingdevelopedThe output terminal signals are maintaineduntil the nesttrigger signal is fed tothe flip-flop. t

Flip-flop 131 is responsive to a binary sip'ral on terminal samples arean be derived autornatially in response to system variables,sothatwiththesysternoperatinginastadystateeond'nion. every error sampleis taken; with the system operating in a transient mode. however. onlyone out ofevery m error saroples is utilized. For the high sampling ratea binary one signal is coupled to terrnirtal 132. while a binary zero isfed tothe terminal for the slower sampling rate. The binary signalcoupled to terminal 132 is fed directly to the set input of flip-flop131 whilethercsetinputoftheflip-flopisresponsivetoan'nverted replig ofthe signal at terminal 132. as coupled through inverter 133. The outputof flip-flop 131 is fed to AND gate 134 through inverter 135. AND gate136 and inverter 137. AND gate 134 is also responsive to the errorindicating output signal of flip-flop 76. HG. 3. Thereby. theoutputofANDgate 134isanexactreplicaoftheerror signal derived fromflip-flop 76 whenever flip-flop 131 is activated to the set state.Hipf'lop 131 is triggered into the set state at the end of each samplingperiod defined by shift registu 91. in response to the trailing edge ofthe shift register D state output. ascoupled through inverter 112 anddifferentiator 113.

With flip-flop 131 in a la'nary zero state. only one out of every inerror samples is coupled through AND gate 134. This occurs because ANDgate 134 is responsive to the output of AND gate 136. having an inputfed by inverter 95, as well as inverter 135. With a binary zero statederived from flip-flop 131. a binary one can be derived from inverter137 only in response to flip-flop 93 being in a binary one state. Thebinary one state is derived from flip-flop 93, however. at a frequencyof llm of the sampling rate for the error signal because of counter 94.

As the error sampling rate changes. it is also necessary to change thegain for the drive circuit of the satellite magnetic torque: 41. For ahigh sampling rate. the gain of the torques processed that is applied toinverter 110. If the output of indr ve circuit should be lea than for aslow error sampling rate.

To synchronize the gain for the magnetic torquer 1 with the samplingrate for the error signal derived by FIG. 3, 3-K flipflop 136 isprovided. The set input of flip-flop 136 is directly rmponsive to theoutput of flip-flop 131, while the reset input of flip-liop136 is aninverted replica of the flip-flop 131 output, as derived by invertercircuit 135. Flipfiop 136 is triggered in parallel with flip-flop 13!.and thereby is respons've to negative going transitions derived fromstage D of shift register 91. The output of flip-flop 135 is coupledthrough inverter 137 to terminal 138, which has an output ing with theoutput of inverter 135, but delayed therefrom by the time it takes shiftregister 91 to cycle through activations of stage D between adjacentcontrol signal intervals. The delay interposed between the outputs ofinverters 13S and 137 is introduced because the sampling error output ofAND gate 134 is not fed into magnetic torquer 41 by the circuitry ofFIG. 6 until after the next corrrplete activation cycie of shiftregister 91.

Consideration is now given to the circuit diagram of FIG. 6. In FIG. 6.the weighting coefficient networks Fl -17, of H6. 1 are replaced withthree-stage preset counter 151, while 12- bit up-down binary counter 152performs the function of serial accumulator 23. Counter 152 responds tothe variable duration error samples derived from the output 0. AND gate134 at a rate dependent upon the preset count stored in counter 151. Tothis end, the frequency division factor ofcounter 151 on a constant orreference frequenq fed thereto from pulse osa'llator 168 (typiallyhaving a frequency of 1200 Hz. for a 30 r.p.m. rotation rate ofsatellite 13) is determined by stages A-Dofshift re 'ster91.FlG.5.

Stages A-D of shift register 91 are interconnected with the stages ofcounter 151 by logic network 153 to introduce the desired frequencydivision or weighting factors for the four different sampling intervalswithin a complete control signal interval. For the first and thirdsampling periods the frequency factors are both one-sixth. while for thesecond and fourth periods, the factors are one-third and one-half,respectivel'y. 'lhis selection establishes the desired weighting factorproportionalityfactorratios corresponding with lFZrL=l rl==L l rl= l ll= To establ'nh the desired frequency division for the difi'erentsampling periods, network 153 includes a direct conin mo GATEISLhIvingafddtherOt-ttprt which ism-maltymaintaktedatabinaryonestateasseeniru'ra'l'heoutputof Ah'Dgate 181, asignal havinganumberofpulscs withineach sampling period equal to theproduce 85, is applied to the input of 12-bit up-down binary counter152.

Counter $52 includes four control input terminals for.clearingthecounter to new state; enablingthe counterto be set;increas'ng the stored count :1 response to each output pulse of A.\'Dgate 181; and reducing the stored count in response to each outputpulseofAND gate 181. The coroner 1S2 incluc'z a control output terminal toindicate when it is in a zero state. as well as a control outputterminal to indicate when ithasreached themaximurncomtwhichitiscapableofstoring. a counter saturation condition.

Binary counter 152 is cleared to a zero state after each controlsiptalinterval habeeneompletedAn indicationota control signal intervalhaving been completed is derived on lad 180 by digitaLto-analogconverter 182 after the converter ha been driven with the nine leastsignificant outputbitsofCormterlSl'l'heloadcorhpletecutputsignald'coonecuon to the secondstage ofcounter 151 from stage B of shift reg'ser 91. This connectionintroduces a divide by three frequency division factor on the referencefrequency signal applied to the input of the counter for the secondsampling period. Since the B and B, weighting factors are one-halfthatof the B, weighting factor, the frequency division introducedinresponsetoshiftreg'sterfl beingsettostagesAandCis sin To establish thedivide by six factor. the A and C stage output: of register 91 are fedto inverter gates 154 and 155. respectively. The outputs of gates 154and 155 are applied to AND gates I57 and 158, which feed the first andthird stages ofcounter 151 through inverter 159 and 160, rewectively. Inresponse to the first and third stages ofcounter 151 being set, thecounter introduces a divide by six frequency division factor on theinput signal thereof. To introduce a divide by two frequency divisionfactor on the input of counter 151. commensurate with the B. weightingfactor, the output of stage D of register 91 is coupled through inverter156 to AND gate 158, which drives the first stage ofcounter 151 throughinverter I60.

Counter 151 thereby generates a clock rate inversely proportional to theB weighting factor of a particular sampling factor for that interval andthe error signal magnitude for the period is proportional to the widthof a rectangular wave form,

multiplication of the error signal and weighting factor can be performedby performing a logic AND operation. To this end the weighting factorindicating output of counter 151 is combined with the error indicatingoutput of flipilop 76, FIG. 3,

verter 182 '5 fed to terminal 183 and appli s! directly to the clearinput terminal ofbinary counter lfil'lhe load complete signal onterminal 183 is also applied through inverter 185 to differentiate-r185. the output of which fwd: the counter 152 set input terminal.Difierentiator 185 thereby feeds a constant duration. positive pulseinto the counter set input terminalaftertheelearcontrolvohagehasbeenrernovedfrorncouner152andthecamterisintheclearedstate.

Counter 152 is now in a zero state, whereby a binary one signalisderivedtherefromon lead 186.1l'rebinaryonesignal on lead1S6isapplicdzanenable signaltothe UP inputterminal of tip-down binarycounter 152 via inverter 187. AND gate 188 and inverter 189. immediatelyalter counter 152 is activated to the UPcount state, a clear inputsiptal is supplied to 8-bit buffer storage register 191 via inverter 192anddiffcrentiator 193, with the inverter being driven in response to theoutput of difi'erentiator 185. 8 bit buffer storage rep'ster 191 isselectively connected to the second through ninthstagcsofcctmterlflinrcsporsetotl'teloaddigitalconvertercattrolsignaloccurringattheendofeachcontmlsignal interval coupled to lead 194 from in erter 116, FIG. 5.

Sirnultanearsly with the contents of the second through ninth stages ofcounter 152 being gated into register 191, digital-to-analog converter182 is fed with nine bits from the least nine significant stages (stagesone to nine) ofcounter 152 in response to the load digital-to-analogconverter signal on lead 19-1. Thereby, upon completion of a controlsiptal interval, converter 182 is fed with an indication ofthe controlsiptal value. U, and register 191 stores a binary signal which an beequated with U/Z after appropriate processing. It I only necessary tofeed the nine lmt sign'n'scant bits of counter 152 to register 191 andconverter 182 because the value ofU at the end of: control signalinterval never exceeds that magnitude, but it may be greater than thanmagnitude prior to completion d the interval necessitating the use of12-bit counter 1S2.

Thesignalstoredinregister 191 isfedbacktothelcasteight significant bitstages of counter 152 atter digital-to-analog converter 182 derives itsload complete signal to effectively Ihifiitsvaluetothe right oneplaceandcauseaU/Zsignalto be derived. To this end. the stages of register 191are selec tively connected to the first eight stages ofcounter 152 toload these counters. Coupling between the output of register 191 and theleast eight significant bit stages of counter 152 is in response to theoutput of difierentiator 193, driven by inverter 192 which is in turnresponsive to the output of differentiate: 185. Counter 152 is therebyset to a signal indiefive of the control signal magnitude for theprevious control signal interval divided by two prior to any errorsignals being fed thereto, i.e., prior to the initiation of the firstsampling period during the next control signal interval.

Once 12-bit up-dovm binary counter 152 has been loaded with the controlsignal derived from the previous control signal interval UJZ, the rimsampling period ofthe ten con trol signal interval is initiated. it isto be recalled that during the first sampling inter al. stage A of shiftregister 91 is activated. whereby the output of AND gate 109 isindicative of the polarity of the incremental change in the value of thecontrol sigtal due to the first sample. Dre output ofgate to; is fed tothe UP and DOWN input control terminals of counter l$2 via terminal B5and logic network 196.

It is broad!y the function of logic network 196 to compare the sign orpoiarity ofthe incremental change in the value of the control signal, asfed to terminal 195, with the polarity of the value of U stored incounter 152 to derive up-down command signals for the counter. To storevalues indicative of the sigt of U. network 196 includes a pair of .l-Kflipfiops I97 and 198 for deriving signals respectively indicative ofthe polarity of the value or U currently in counter 152 and at the endof the previous control signal interval. Flip-flop 197 is triggered onlyin response to counter l52 going through a zero count at s time otherthan while the digital-toanalog load complete circuit is being derivedby converter 182. To this end, the zero count indicating output lead 186of counter [52 is coupled to the trigger input of flip-flop 197 via ANDgate 199, which is enabled in respon e to the output of AND gate 181only while an error signal is being coupled through AND gate 181.11:output signal of AND gate 199 is fed through inverter l to an inputterminal of AND gate 202. the other input of which is enabled at alltimes except while a digital-toanalog load complete signal is beingapplied by dii'ferentiator 113, FIG. 5. to terrm'nal 183, by virtueofthe connection of AND gate 202 to the output ofinverter l.

The output of AND pte 202 is fed through inverter 203 to the triggerinput of flip-flop l97, having set and reset inputs rspectivelyrspqrsive to positive and negative polarity inditations ofthe change inthe value ofU. as coupled to terminal B5. The signal coupled to terminal195 is fed to the set input terminal of flip-flop I97 via inverter 204and AND gate 205. the other input of which is enabled at all timesexcept while the digital-to-analog load complete signal is being coupledto terminal 183 by virtueofthe connection of the other input of AND gate205 to the output ofinverter l8-4.The reset input of flip-flop 19'] isresponsive to negative polarity indications of the change in the valueofU (AU) for the sample being considered by coupling the signal atterminal I95 through AND gate 207 and inverter Hi8 to the flip-flopreset input. AND gate 207 y is enabled simultaneously with AND gate 205because of its connection to the output of inverter lb.

Became flip-flop 197 is triggered in response to changes in polarity ofthe value of U stored in counter 152 when the counter goes throuflr azero. it effectively stores the polarity of the value of U at the end ofa complete control sig'tal interval. This value is transferred toflip-flop 198 while digital-toanalog converter l82 is being loaded inresponse to the output signal of inverter 116. F135. To this end. theoutput signal of inverter "6 is coupled via lead 194 to the triggerinput oftlipflop I98. having set and reset inputs responsive to theoutput of flip-flop 197. The set input of flip-flop 193 is directlyconnected to the output offlip-flop 197, while the reset input offlip-flop 193 is responsive to an inverted replica of the flip-flopoutput, as through inverter 209.

The sign of AU for the currently processed sampling interval -Fned withthe sign of AU signal for the just previously handled sampling intervalin a network of inverter and AND gates to drivethc updown control inputterminals of counter 152. To this ad. the AU signal at terminal l95 iscombined with the AU output of flip-flop X97 in AND gate 211, whileinverted replicas of the siptals at terminal 195 and the output offlip-flop 197 are fed to AND gate 212 via inverters 2l3 and 2.99,reqaeetively. The outputs of AND gates 211 and 212 are fed throughinverters 2l3 and 214, respecti ely. to inputs of AND gate 181, whidrives the UP and D'JWN input control terminals ofcourtter 152, asdescribed supra.

To consider an exemplary case as to the manner by whtclt of the errorweighting coefhcient for the first sample is positive and the value of Ufor the previously completed control signal interval is negative. Forsuch a situation, counter 152 shouldbeactivatedtoscountdownrnodebccauseoftheopposit: polarities of the two signalsconseartively applied thereto. To achieve this result, a binary onesiytal is applied to terminal 195 to enable AND gate Zll and disable ANDgate 212. While the binary one AU signal is fed from terminal 195 to ANDgate 211. flip-flop I97 derives a binary zero outpuLtoindicatetl'iernintevalueofuatthemdoftbepreviouseontrolsignal intervaLThebinaryonesignalatterminal land .the binary zero output of flip-flop 197result in a binary zero being derived from the output of AND gate ill.Since AND gate 212 is deriving a binary zero sigtal and inverter 187 isderiving a binary one signal while a binary zero is being derived fromAND gate 2l 1. a binary one output is generated byANDgateISStosetivatecounterISZtodrecountdown state One further feature of thecirwitry associated with counter 152 is that the count is mainta'ned atthe maximum level. once saturation has been reached until a countdowncontrol signal is derived. To this end. the counter includes an outputlead 215 on whichthere isderived sbinaryone valueaslongasthe counter hasnot reached maxirntt'tt count. The signal on lead 215 is combined withthe output ofAND gate 188. as coupled through inverter 215, in AND gate2". The output of AND gate 2" is fed through inverter 2l8 to an input ofAND gate 181. Thereby, inverter 218 derites a binary one signal toensble AND gate [81 as long: oourrtersaturation has not been reached.With coantersaturation having been reached. a binary zero ifden'ved fromthe output ofinverter 2l8 to decouple counter 152 from the error signalsnormally fed through the AND gate. Counter 152 rentals decoupled fromthe error siprals until adown count indicatingsignal isderived asabinaryoneoutputofANDgate l88.lnresponsetoadown count command signalbeing supplied to count: I52, the

counter will be removed from a saturated state and therefore in responseto the load digital-to-analog converter signal' derived bydifferentiator 113. FIG. 5. After the output of counter 152 has beenloaded into converter 1222 and the converter is deriving an outputsignal cornmenarrate therewith, the converter generates a load completesignd on lead to initiate a new control signal interval.

The analog output of converter I82 feeds coil 220 cfmagnetic torquer 41through network 221. Network 22l include switches 222 and 223 resporsiveto the peaodically changed output of digital-to-analog converter I82.Switches 222 and 223 are responsive to the polarity of U indicationderived from flip-flop 193 to control the polarity of the analog inputto coil 220 of magnetic torquer 41. in response to a positiveindicalion, stored in fliptlop 193, for the sip of U for the previouslycompleted control signal interval being positive, switch 222 isDifference network 224 thereby derives a constant arnplitude signalhaving a value of U over each control signal interval. The polarity ofthe signal generated by difference netcounter 152 functions, assume thatthe polarity of the produce 75 work 224 is appropriately controlled eventhough a single quadrant digital-to-artalog converter l82 is prodded.The output of difference network 224 is led to coil 225 of magnetictorquer 41 via power amplifier 226. having a wing gain of one. Thesignal derived from power amplifier 226 is selectivel attenuated byresistors 227 and 228 depending upon the gain of the system. as derivedat terminal 138. FIG. 5. For a high gain. with the system operating in atrarsient condition, the output of amplifier 226 is coupled directly tocoil 225 by shunting resistors 227 and 228. To this end. suitches 229and 2.31 are connected in parallel with resistors 227 and 228.respectively. Suitches 229 and 231 are driven in parallel with the highgain signal fed to terminal 138. whereby the switchs are closed inresporse to the high gain signal having a binary one value. For lowgain. as desired in the steady state operating mode. a binary zero isfed to control input terminals d switches 229 and 7.3] through terminalB8 to insert resistors 22'! and 228 into the circuit.

Consideration will now be given to the technique for deriving the values8,-8. for the system of FIG. 2. which can be 20 described by doubleintegration for a period of 2'! seconds. 30

the velocity and position of the plant 2T seconds after the controlsignal was applied thereto can be represented as:

where:

plant at the time being considered;

u, and 9. are respectively the initial velocity and positions! theplant;

r time;

U =the value olthe control sigtal;

U.= the initial value of the control signal;

1' a dummy integration variable; and

K system gain a defined supra.

Integrating. assuming constant values over the interval. mulso gEquation(2) by T. and simplifying yield:

zF -ufl efnu5+e lK2K P)U. (5).

Letting CFKl and adding the control law:

fi u) t-H n) e'K aal o where a and er are state l'eedbaclt coefircients.then yields the closed-loop-system coefircient matrix defined as Tun- 02 Tu TH. 1 0, 2 2 2G 0 nu ll n e e 65 where A is the matrix defining thesystem response at the instant of the Equation (6) control-law update toany set of initial conditions. The output state, q2T seconds, where q isan integer. after a g'ven set of initial conditions. is

u and 6,,- are rapectively the velocity and position of ll: 40

Therefore. ilthe controller parameters (an. a a, and G) can be chosen sothat A has all zero elements. then any initial state vector will bereduced to zero after these control-law updates.

The parameters G and a: are not independent. as can be seen by lettinga; 0 andrewriting Equation (7) as:

Tan- 1 '0 2016; Tu.

Thus. without los ol'generality a can be made equal to l 5 for unityfeedback of the output 8, with 6 left as a free parameter. Now, using roz consider the system response to an initial output displacementwhrchts 0 "-1 (1-'G; )2G 1(l+G )d A necesary condition for finitesettlirtgtirne respomeisthat which yields the set ol'eqrntiorrs 2+n =02G=l/( +fin) 14) that is satisfied by the state feedback ooefficientsCalculating A shows that all the elements of A are zero; therefore.EquationUS) is suflicient as well as necesary for finite settling timerespome. A similar development for a more general second-order plant hasbeen carried out and is reported in the PhD. thesis of James A. Gatlirt,University of Maryland. College Park, Maryland. 1968.

Control-law synthesis involves selecting the weighting factors B ,...,B,so as to make Equations (1) and (6) identical. Using plant model givenby Equations (2) and (3). the calculated values of 9,...,8. during aZT-second interval are V For the control formulation of Equation (24),

4B,=9( l-a4B,), F- Q 48531-368; 5 for which the control-law variancefactor is l6F=8l( I4B,)*+l296( l2B.)+(3l36 (31). Solving for the g gminimum Fyields' I o=1o2 1-4B. +t296 1-2B, +tt(31368.) (32 Multiplying}the appropriate weighting factors and adding yields the control-lawmatrix elements (a'h'rgzmww E5185 2 which produces the weighting factas-an=-lnBn+(n .-i+ +811 n 8 -0333, (33). -u, B,-l-B,,, l-...-l-B (l9).8,-3.083. B.+- ,Q and, for 3 samples, F =l$.5. l dfifimlm. It isinteresting to compare these results with the weighting factors requiredfor the finite settling t me response when G a.,=o. Equatiom (so thenyield and B =2.25.

g t P TI ;,I u+( l-l+ l] 8 7.75,

and Thus, for a given It. Equation (l9) can be solved for the weightingturn that produce the finite settling time matrix "145;

Pmmflm thus, memory of the previous control level is very efl'ective inM my be for reducing the control-law variance factor and noisesensitivity.

When four samples are taken, Equations (l9) become -a,,ll 4B+3B,-+2B,+B,a], a 0 l 2 B. ng=&+B,+B,+8,, 0 l 1 l S7,=l6B,+9B,-HB,+B 154 M One way to handle four samples and provide the easily implewhichhas the inverse 3S mented coefficients utilized in the system describedin con- B M M 1 an junction with FIGS. 2-6 is to use the constraintrelationship B -l 2 O c [B1] 1 -1 o] 3] (23) H r OSOXhIlEQLBUOIE(BS)MUC8O to yield BM B,=-3 and 8,:4 so that the resulting finitesettling time control-law formulation is Al -49 136,! 24). Thecontrol-lav variance factor, F, a measure of noise sensitivity. isdefined as l I: BJ'Z'IJ'I" Z2 (25) B, 2 o -1 s -6+8B. where q; a thevariance Orin: control signal. u. and 0', a B, a -2 -1 1 3+8B. thevariance otthe output samples. 3 1 1 30-3.) 7-83 which has an inverseand yields. as the required set d PST weighting factors,

F=(4)"(3)=2$ (26). When three or more samples are taken, 8, can be leftas a [filling F Yields the "8 m mud-13W free parameterand used tominimize F after the control law has been fomiulatcd. 'fl'iis involvesreplacing a: in Equation 73= (CI:BI) (2 B.) w with I F=(3)(l i-(ZY-H lY=t$. m rnm value of r is only 30 percent greater than the absoluteminimum as derived in the previously mentioned Thesis so 3a 2 4 6 B tthat the system of ROS. 2-6 has relatively low noise sensitivil l 1 tyand finite settling time within two ZTcontrol signal formu- 1 4 9 Blation intervals.

which has the inverse While there has been described and illustrated onespecific B 5 12 2 3a embodiment of the in ention, it will be clear thatvariations of =34 8 4 the details of construction which are specificallyillustrated 4 2 35 2 3 2 and described may be made without departingfrom the true spirit and scope of the in ention as defined in theappended The FST control-law fonnulation that results is Claim Forexample, the int-enti m can be used to protide dcspin U,-=8,G,+B,6,+B,9|+B.U. control of a dual spin satellite wherein a motoris used to counterrotate a platform on a satellite but rotatable to it.in such an example it is desired to maintain the position of theplatform aligned with the horizon as detected by a horizon sensor on therotatable portion of the satellite. The output ofthe sensor. a pulsetrain similar to that of horizon detector 35. is com pared with areference frequency in a network as illustrated for the cartwheelsatellite to control the platform to the aligned position.

lclaim:

I. A sampled data controller for a plant having a known input vs. outputresponse, said controller being responsive to a reference input.comprising means responsive to the plant out put response and referenceinput for deriving an error signal, mans responsive to the error signalfor deriving a control signal for the plant. said control signal beingderived for a control signal formulation interval, means for controllingthe plant in response to the control signal. said mars for derivingincluding means for mmbining signals proportional to the control signalof a previous formulation interml and signals proportional to the errorsignal magnitude at different times within interval for the controlsigral being formulated.

2. The controller of claim 1 wherein said means for deriving includesmeans for accumulating the signals proportional to the error signalsonly during the interval and the control signal of the previouslyformulated control signal.

3. The controller of claim 2 wherein said mans for deriving includesmeans for introducing proportional factors on the error signalmagtitudes, said factors being a function of the occurrence time of theerror signal within the formulation interval and the plant input versusoutput response to provide futite settling time of the plant.

4. The controller of claim 2 wherein said means for deriving includesmears for introducing n (where n is an integer equal to or greater than2) proportionality factors on the error signal itudes. said factorsbeing a function of the occurrence time of the error signal within theformulation interval and the plant input versus output response toprovide finite settling time for the plant, at least two of said factorsbeing different.

5 The controller of claim I wherein said means for deriving includesmeans for introducing proportional factors on the 40 error signalmagnitudes, said factors being 'a function of the occurrence time of theerror signal within the formulation interv-al and the plant input versusoutput response to provide finite settiing time for the plant.

6. The controller of claim I wherein said means for deriving includesmeans for introducing n (where n is an integer equal to or greater than2) proportionality factors on the error signal magnitudes, said factorsbeing a function of the occurrence time of the error s'gial within theformulation interval and the plant input versus output resporee toprovide finite settling time for the plant. m least two of said factorsbeing different.

7. The system of claim 1 wherein said means for deriving includes meansfor sampling the error signal a plurality of tima within each controlsignal formulation interval to derive the 18 proportional to the controlsign! of the previous formulation interval.

8. The system of claim 7 wherein said combining means includes means foraccumulating the sampled signals only over each control signalformulation interval.

9. 1e system of claim 7 wherein said deriving means includes a singlesignal multiplying means responsive to the sampled error n'grals forapplying variable proportionality constants to difierent error samples,as a function of the error sample otxurrence time within the formulationinterval.

to. A system for mntrolling in mponse to a reference wave train having areference frequency the position of a continuously moving body havingmeans for deriving a variable wave train having variable phase andfrequency a a function of the body position and rate of movementcomprising means for comparing the reference and variable wave trains toderive an error signal having a frequency equal to the referencefrequency. means responsive to a plurality of cycles of the error signalfor formulating a single control signal magnitude for the position ofthe body. said lat named means including: means responsive to apreviously formulated control signal magnitude. and means forintroducing variable weighting factors on different cycles of the errorsignal as a function of cycle number within the control s'gnalformulation interval; and meansforcontrollingthe positionofthe bodyinresponse to sequentially derived control signal magnitudes.

11. The system of claim 10 wherein: said error signal deriving meansincludes means for deriving means for deriving a pulse width modulatedwave for each of said cycles, aid means for introducing includes meansfor deriving a variable number of pulses during each of said cycles,said number being related to the weighting factor for each cycle, andsaid means for deriving includes means for combining said variablenumber of pulses with said pulse width modulated wave in accordance withthe logial AND function.

lZThesystemofclairnllwhereinsaidderivingmaroin- I eludes updovn countermeans for accumulating the output of said logical AND means only overeach control signal formulation interval, and means for controlling thecounter counting direction in raponse to the polarity of the errorsignal.

13. A system for controlling the position of: body on acoutinuouslyrotau'ng satellite compr sing a reference wave train source having areference frequency, position sensing means for deriving a variable wavetrain having variable phase and frequency 83 function of the bodyposition and rate of movement. means for comparing the reference andvariable wave trains to deri e an error signal having a frequency equalto the reference frequency, means responsive to a plurality of cycles ofthe error signal for formulating a single control signal magnitude forthe position of the body. said 1st named means including: meansresponsive to a previously formulated control signal magnitude, andmeans for introducing variable weighting factors on different cycles ofthe error signal as a function of cycle number within the control signalformulation lgnals Proportional lhc 938ml magnlluks and interval;andmeansfor controlling the position of the bodyin sampling the previouscontrol signal magnitude once during each control signal formulationinterval to derive the signal response to sequentially derived controlsignal magnitudes UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTIONPatent No. 3, 578, 957 Dated May 18, 1971 lnventofls) James A. Gatlin Itis certified that: error appears in the above-identified patent and thatsaid Letters Patent are hereby corrected as shown below:

The line designation numbers, located between the columns,

in many instances do not iden tify the correct lines. Accordingly,

the lines referred to below are the actual line number--the designatedline numbers are not to be used for reference purposes.

Column 2, line 1, after "signals" there should appear -are--,

Column 3, line 15, "l7 should appear as l7 II II a line 20, t shouldappear as t +t lines 30 and 31, "B (in both instances) should appear as-B line 32, "17 should appear as -l7 and line 52, "B B B a (R-C) shouldappear as --B E B (R-C) Column 4, line 1, B ,E should appear as --B Eand line 68, "1/ 2 should appear as -l/s FORM PC3-1050 (10-69] USOMM DCooa-nhpaq b u s GOVIINHINI unnms ornc: 1 an 0-in-3 UNITED STATES PATENTOFFICE CERTIFICATE OF CORRECTION Patent No. 3 I 7 957 Dated M y 18, 1971Inventor(s) J m A. Gatlin PAGE 2 It is certified that error appears inthe above-identified patent and that said Letters Patent are herebycorrected as shown below:

Column 5, line 2, "K/ Z" should appear as -K/s Column 9, line 48, "Bshould appear as --B Column 10, line 23, "185" should appear as -l84--.

Column 12, lines 29 and 30, "countersaturation (in both instances)should appear as --counter saturation-.

Column 13, line 52, (in Equation 5) "az" should appear as and line 54,"G=Kt should appear as --G=KT Column 15, line 17, (Equation 19) "-a B 13. .+B,

should appear as -a B B lane 18, -a B y G should appear as line 20, (20)(second occurrence) should not appear;

FORM PO-IOSO 0-69) uscomwoc 6OS76-F'69 UNITED STATES PATENT OFFICECERTIFICATE OF CORRECTION Patent No. 3 578, 957 Dated May 18 1971Inventor(s) James A. Gatlin AGE 3 It is certified that error appears inthe above-identified patent and that said Letters Patent are herebycorrected as shown below:

line 44, (Equation 24) "-UZT 4 2 /3 l%U 3 should appear as U E\ 46 36+.-U line 49, (Equation 25 "F =Z (59 :01; /01,}

2 .2 -2 should appear as F (B U Ag .3 line 51, "O and "02 respectively,should appear as O'J" and O and line 54, "F=(4) 3 25" (Equation 26should appear as --F=(4) (3) 25--.

Column 16, line 2, "4B 9(l-a4B should appear as 4B line 12, "(B2016/1944 0.5185" should 0 OPT appear as (B 2016/1944 0.5l85;

o OPT line 27, "F=l45" should appear as F l46-;

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION May 18, 1971Patent No. 3 I 9557 Dated PAGE 4 n en fl James A. Gatlin It is certifiedthat error appears in the above-identified patent and that said LettersPatent are hereby corrected as shown below:

"-a fl m1a 3B3 2B2 B1211" should line 32,

appear as a 2 [43 3B 2B B line 45 "2 7-3" should appear as --2y and line59, U 36 a2 9 6 l should I appear as U 36 6 26 6 +ZU Signed and sealedthis 9th day of May 1972.

(SEAL) Attest:

EDWARD M.FLE'TCHER, JR. ROBERT GOT'I'SCHALK Attesting OfficerCommissioner of Patents USCOMM-DC 60376-5 69 ORM PO-IOSO {10-69) a u soovsnnmm Pamimc. ornc: I959 0-355-114

1. A sampled data controller for a plant having a known input vs. output response, said controller being responsive to a reference input, comprising means responsive to the plant output response and reference input for deriving an error signal, means responsive to the error signal for deriving a control signal for the plant, said control signal being derived for a control signal formulation interval, means for controlling the plant in response to the control signal, said means for deriving including means for combining signals proportional to the control signal of a previous formulation interval and signals proportional to the error signal magnitude at different times within interval for the control signal being formulated.
 2. The controller of claim 1 wherein said means for deriving includes means for accumulating the signals proportional to the error signals only during the interval and the control signal of the previously formulated control signal.
 3. The controller of claim 2 wherein said means for deriving includes means for introducing proportional factors on the error signal magnitudes, said factors being a function of the occurrence time of the error signal within the formulation interval and the plant input versus output response to provide finite settling time of the plant.
 4. The controller of claim 2 wherein said means for deriving includes means for introducing n (where n is an integer equal to or greater than 2) proportionality factors on the error signal magnitudes, said factors being a function of the occurrence time of the error signal within the formulation interval and the plant input versus output response to provide finite settling time for the plant, at least two of said factors being different.
 5. The controller of claim 1 wherein said means for deriving includes means for introducing proportional factors on the error signal magnitudes, said factors being a function of the occurrence time of the error signal within the formulation interval and the plant input versus output response to provide finite settling time for the plant.
 6. The controller of claim 1 wherein said means for deriving includes means for introducing n (where n is an integer equal to or greater than 2) proportionality factors on the error signal magnitudes, said factors being a function of the occurrence time of the error signal within the formulation interval and the plant input versus output response to provide finite settling time for the plant, at least two of said factors being different.
 7. The system of claim 1 wherein said means for deriving includes means for sampling the error signal a plurality of times within each control signal formulation interval to derive the signals proportional to the error signal magnitudes and for sampling the previous control signal magnitude once during each control signal formulation interval to derive the signal proportional to the control signal of the previous formulation interval.
 8. The system of claim 7 wherein said combining means includes means for accumulating the sampled signals only over each control signal formulation interval.
 9. The system of claim 7 wherein said deriving means incluDes a single signal multiplying means responsive to the sampled error signals for applying variable proportionality constants to different error samples, as a function of the error sample occurrence time within the formulation interval.
 10. A system for controlling in response to a reference wave train having a reference frequency the position of a continuously moving body having means for deriving a variable wave train having variable phase and frequency as a function of the body position and rate of movement comprising means for comparing the reference and variable wave trains to derive an error signal having a frequency equal to the reference frequency, means responsive to a plurality of cycles of the error signal for formulating a single control signal magnitude for the position of the body, said last named means including: means responsive to a previously formulated control signal magnitude, and means for introducing variable weighting factors on different cycles of the error signal as a function of cycle number within the control signal formulation interval; and means for controlling the position of the body in response to sequentially derived control signal magnitudes.
 11. The system of claim 10 wherein: said error signal deriving means includes means for deriving means for deriving a pulse width modulated wave for each of said cycles, said means for introducing includes means for deriving a variable number of pulses during each of said cycles, said number being related to the weighting factor for each cycle, and said means for deriving includes means for combining said variable number of pulses with said pulse width modulated wave in accordance with the logical AND function.
 12. The system of claim 11 wherein said deriving means includes up-down counter means for accumulating the output of said logical AND means only over each control signal formulation interval, and means for controlling the counter counting direction in response to the polarity of the error signal.
 13. A system for controlling the position of a body on a continuously rotating satellite comprising a reference wave train source having a reference frequency, position sensing means for deriving a variable wave train having variable phase and frequency as a function of the body position and rate of movement, means for comparing the reference and variable wave trains to derive an error signal having a frequency equal to the reference frequency, means responsive to a plurality of cycles of the error signal for formulating a single control signal magnitude for the position of the body, said last named means including: means responsive to a previously formulated control signal magnitude, and means for introducing variable weighting factors on different cycles of the error signal as a function of cycle number within the control signal formulation interval; and means for controlling the position of the body in response to sequentially derived control signal magnitudes. 